What is STT MRAM

STT-MRAM: Toshiba is working on a superior alternative to SRAM

Toshiba's research department is working on using STT-MRAM as cache memory for processors and SoCs. It is intended to replace the currently used SRAM, which is extremely fast, but is a weak point, especially in the mobile sector, due to the space required and the relatively high power consumption.

The high power consumption is due, among other things, to the fact that SRAM requires a lot of space and has to contend with leakage currents. In addition, SRAM is a volatile memory that requires a constant power supply so that the data is retained in the cache. As the cache size increases, so does the energy requirement.

In contrast, STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) is a non-volatile memory that stores data for a long time even when it is switched off. In combination with the relatively high performance, STT-MRAM has long been mentioned as a possible successor technology for both DRAM and NAND flash.

Magnetic properties are used in STT-MRAM to write and save the data, more precisely the magnetic tunnel resistance (TMR), which occurs in magnetic tunnel contacts (MTJ). If you want to write data, the magnetic orientation of a thin magnetic layer in the MTJ element is changed with the aid of a spin-polarized current. To read the data, the resistance of the element is measured, which depends on the magnetization of the MTJ.

The circuits of the test chip from Toshiba allow access times of 3.3 nanoseconds. Although this does not come close to the performance of conventional SRAM, the STT-MRAM requires around 80 percent less energy.

In order to achieve this, besides other optimizations in reading and writing, the peripheral control circuits of the memory had to be revised, which are normally always supplied with power. The aim was to be able to switch it on and off again as quickly as possible so as not to lose too much power. In particular, the time it takes to restore power is critical as it affects access latencies. For this purpose, the memory area was divided into seven regions with their own load switch, which can be deactivated independently of one another.

The shortest measured time for restoring the power supply after switching off is specified as 22 ns, which is shorter than the average waiting time for cache access, which Toshiba specifies as 30 ns.

As a goal of the project, which will run until the end of the fiscal year 2015, Toshiba states the further improvement of the technology in order to reduce the total power consumption of processors to less than a tenth compared to conventional circuits.

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